As many people know, computers or microprocessors operate by executing a programmed sequence of instructions. A computer instruction is a machine code that tells the computer to perform a particular operation. In this respect, every computer is designed to operate in accordance with a defined instruction set architecture (ISA). Unfortunately, most computers are limited to running programs that are only compatible with a single instruction set architecture. This means that programs written using instructions from a different ISA cannot be executed on that machine.
Today, researchers face the challenge of building a computing machine that is capable of incorporating two or more widely divergent instruction set architectures onto a single piece of silicon. One of the primary problems, which must be addressed to solve this problem, is the wide semantic gap that exists between different instruction set architectures.
To better appreciate the problem faced by researchers working in the field of computer design and architecture, one must first understand the basics of how instructions are processed within the machine. The architecture of many processors implement programmed instructions--often referred to as macroinstructions--by sequences of microcode statements. That is, usually a macroinstruction is decoded by decoding logic into a sequence of micro-instructions or micro-operations (conveniently termed "micro-ops" or "uops" for short). These uops are executed by the processor's core logic. By way of background, an explanation of micro-ops is provided in pending U.S. patent application Ser. No. 08/205,039, filed Mar. 1, 1994, entitled, "Computer with Distributed Program Control".
An additional factor complicating the problem is that microarchitectures associated with different ISA's are constrained to work within the boundaries of instructions having particular sizes. Decoding and executing instructions from widely divergent ISAs therefore requires many different microcode flows. Due to the great dissimilarities between different instruction set architectures, the amount of microcode required to accommodate and express all of the various instructions explodes beyond reasonable proportions. This, in turn, translates directly into an excessively long microcode development time.
Thus, there exists a need for an apparatus and method for implementing a particular instruction set on a machine that was not designed specifically for that purpose. To put it another way, there is a need for a mechanism that would simplify and shorten the microcode development process for a machine that could execute instructions from different ISAs. Ideally, the machine should be implemented without incurring the significant amount of silicon die area that would be required to implement widely-divergent instructions sets by simply taking a "brute force" approach to the problem.